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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2006, zarlink semiconductor inc. all rights reserved. a full design manual is available to qualified customers. to register, please send an email to timingandsync@zarlink.com. features ? synchronizes with standard telecom system references and synthesizes a wide variety of protected telecom line interface clocks that are compliant with telcordia gr-253-core and itu-t g. 8 1 3 ? internal apll provides standard output clock frequencies up to 622.08 mhz that meet jitter requirements for interfaces up to oc-192/stm-64 ? programmable output synthesizer generates clock frequencies from any multiple of 8 khz up to 77.76 mhz in addition to 2 khz ? digital phase locked-loop (dpll) provides all the features necessary for generating sonet/sdh compliant clocks including automatic hitless reference switching, automatic mode selection (locked, free-run, holdover), and selectable loop bandwidth ? provides 3 reference inputs which support clock frequencies with any multiples of 8 khz up to 77.76 mhz in addition to 2 khz ? provides 3 sync inputs for output frame pulse alignment ? generates several styles of output frame pulses with selectable pulse width, polarity, and frequency ? configurable input to output delay, and output to output phase alignment ? flexible input reference monitoring automatically disqualifies references based on frequency and phase irregularities ? supports ieee 1149.1 jtag boundary scan june 2006 figure 1 - block diagram dpll_mod_sel tck tdo tdi tms trst_b dpll_holdover dpll_lock sck so si dpll rst_b cs_b diff_en reference monitors ref sync ref0 ref1 ref2 sync0 sync1 sync2 int_b sdh_clk sdh_fp p_clk p_fp ref2:0 sync2:0 ref_&_sync_status controller & state machine spi interface sonet/sdh apll diff_clk_p/n ieee 1449.1 jtag master clock osco osci sdh_filter filter_ref0 filter_ref1 programmable synthesizer ZL30117 sonet/sdh oc-48/oc-192 line card synchronizer data sheet ordering information ZL30117ggg 64 pin cabga trays ZL30117ggg2 64 pin cabga* trays *pb free tin/silver/copper -40 o c to +85 o c
ZL30117 data sheet 2 zarlink semiconductor inc. applications ? amcs for advancedtca tm and microtca systems ? multi-service edge switches or routers ? dslam line cards ? wan line cards ? rnc/mobile switching center line cards ? adm line cards
ZL30117 data sheet table of contents 3 zarlink semiconductor inc. 1.0 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.1 dpll features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2 dpll mode of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.3 ref and sync inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.4 ref and sync monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.5 output clocks and frame pulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.6 configurable input-t o-output and output-to-out put delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.0 software configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.0 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
ZL30117 data sheet list of figures 4 zarlink semiconductor inc. figure 1 - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2 - automatic mode state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 3 - reference and sync inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 4 - output frame pulse alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5 - behaviour of the guard soak ti mer during cfm or scm failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 6 - output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 7 - phase delay adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
ZL30117 data sheet list of tables 5 zarlink semiconductor inc. table 1 - dpll features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 2 - set of pre-defined auto-detect clock frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 3 - set of pre-defined auto-detect sync frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 4 - output clock and frame pulse frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 5 - register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
ZL30117 data sheet 6 zarlink semiconductor inc. changes summary the following table captures the changes from the february 2006 issue. page item change 20-21 software register description changed the naming and description of the frame pulse delay offset register s to clearly show that they form a 22-bit register spread out over 3 8-bit registers. the 22-bit regist er must be considered a multi-byte register during a read or write operation. this affects registers 0x40-0x42, and 0x58-0x5a.
ZL30117 data sheet 7 zarlink semiconductor inc. pin description pin # name i/o type description input reference b1 a3 b4 ref0 ref1 ref2 i d input references (lvcmos, schmitt trigger). these are input references available for synchronizing output cloc ks. all three input references can be automatically or manually selected using software registers. these pins are internally pulled down to vss. a1 a2 a4 sync0 sync1 sync2 i d frame pulse synchronization references (lvcmos, schmitt trigger). these are the frame pulse synchroniz ation inputs associated with input references 0, 1 and 2. these inputs acc ept frame pulses in a clock format (50% duty cycle) or a basic frame pulse form at with minimum pulse width of 5 ns. these pins are internally pulled down to v ss. output clocks and frame pulses d8 sdh_clk o sonet/sdh output clock (lvcmos). this output can be configured to provide any one of the sonet/sdh cloc k outputs up to 77.76 mhz. the default frequency for this output is 77.76 mhz. d7 sdh_fp o sonet/sdh output frame pulse (lvcmos). this output can be configured to provide virtually any style of output fr ame pulse synchronized with an associated sonet/sdh family output clock. the de fault frequency for this frame pulse output is 8 khz. g8 p_clk o programmable output clock (lvcmos). this output can be configured to provide any frequency with a multiple of 8 khz up to 77.76 mhz in addition to 2 khz. the default frequency for this output is 2.048 mhz. g7 p_fp o programmable output frame pulse (lvcmos). this output can be configured to provide virtually any style of output frame pulse associat ed with p_clk. the default frequency for this frame pulse output is 8 khz. a7 b8 diff_clk_p diff_clk_n o differential output clock (lvpecl). this output can be configured to provide any one of the available sdh clock fr equencies. the default frequency for this clock output is 622.08 mhz. control g5 rst_b i reset (lvcmos, schmitt trigger). a logic low at this input resets the device. to ensure proper operation, the device must be reset after power-up. reset should be asserted for a minimum of 300 ns. b2 dpll_mod_sel i u dpll mode select (lvcmos, schmitt trigger). during reset, the level on this pin determines the default mode of operati on of the dpll (normal or freerun). after reset, the mode of operation can be controlled directly with these pins, or by accessing the dpll_modesel register through the serial interface. this pin is internally pulled up to vdd. b3 diff_en i u differential output enable (lvcmos, schmitt trigger). when set high, the differential lvpecl driver is enabled. when set low, t he differential driver is tristated reducing power consumption. this function is also controllable through software registers. this pin is internally pulled up to vdd.
ZL30117 data sheet 8 zarlink semiconductor inc. status e1 dpll_lock o lock indicator (lvcmos). this is the lock indicator pin for the dpll. this output goes high when the dpll?s output is frequency and phase locked to the input reference. h1 dpll_holdover o holdover indicator (lvcmos). this pin goes high when the dpll enters the holdover mode. serial interface c1 sck i clock for serial interface (lvcmos). serial interface clock. d2 si i serial interface input (lvcmos). serial interface data input pin. d1 so o serial interface output (lvcmos). serial interface data output pin. c2 cs_b i u chip select for serial interface (lvcmos). serial interface chip select. this pin is internally pulled up to vdd. e2 int_b o interrupt pin (lvcmos). indicates a change of devi ce status prompting the processor to read the enabled interrupt se rvice registers (isr). this pin is an open drain, active low and requires an external pulled up to vdd. apll loop filter a5 sdh_filter a external analog pll loop filter terminal. b5 filter_ref0 a analog pll external loop filter reference. c5 filter_ref1 a analog pll external loop filter reference. jtag and test g4 tdo o test serial data out (output). jtag serial data is output on this pin on the falling edge of tck. this pin is held in high impedance state when jtag scan is not enabled. g2 tdi i u test serial data in (input). jtag serial test instructions and data are shifted in on this pin. this pin is internally pulled up to vdd. if this pin is not used then it should be left unconnected. g3 trst_b i u test reset (lvcmos). asynchronously initializes the jtag tap controller by putting it in the test-logi c-reset state. this pin should be pulsed low on power- up to ensure that the device is in the normal functional state. this pin is internally pulled up to vdd. if this pin is not used then it should be connected to gnd. h3 tck i test clock (lvcmos): provides the clock to the jtag te st logic. if this pin is not used then it should be pulled down to gnd. f2 tms i u test mode select (lvcmos). jtag signal that controls the state transitions of the tap controller. this pin is internally pulled up to v dd . if this pin is not used then it should be left unconnected. master clock h4 osci i oscillator master clock input (lvcmos). this input accepts a 20 mhz reference from a clock oscillator (xo, xt al). the stability and accuracy of the clock at this input determines the free- run accuracy and the long term holdover stability of the output clocks. pin # name i/o type description
ZL30117 data sheet 9 zarlink semiconductor inc. i - input i d - input, internally pulled down i u - input, internally pulled up o - output a - analog p - power g - ground h5 osco o oscillator master clock output (lvcmos). this pin must be left unconnected when the osci pin is connected to a clock oscillator. miscellaneous f5 ic internal connection. leave unconnected. h6 ic internal connection. connect to ground. h2 h7 nc no connection. leave unconnected. power and ground c3 c8 e8 f6 f8 g6 h8 v dd p p p p p p p positive supply voltage. +3.3v dc nominal. e6 f3 v core p p positive supply voltage. +1.8v dc nominal. b7 c4 av dd p p positive analog supply voltage. +3.3v dc nominal. b6 c7 f1 av core p p p positive analog supply voltage. +1.8v dc nominal. d3 d4 d5 d6 e3 e4 e5 e7 f4 f7 v ss g g g g g g g g g g ground. 0 volts. a6 a8 c6 g1 av ss g g g g analog ground. 0 volts. pin # name i/o type description
ZL30117 data sheet 10 zarlink semiconductor inc. 1.0 functional description the ZL30117 sonet/sdh line card synchronizer is a highly integrated device that provides timing and synchronization for network interface cards. the dpll is capable of locking to one of three input references and provides a wide variety of synchron ized output clocks and frame pulses. 1.1 dpll features the digital phase-locked loop synchronizes to one of the qualified references and provides automatic or manual hitless reference switching and a holdover functi on when no qualified references are available. it provides a highly configurable set of features which ar e configurable through the serial interface. a summary of these features are shown in table 1. feature dpll modes of operation free-run, normal (locked), holdover loop bandwidth user selectable: 14 hz, 28 hz, or wideband 1 (890 hz / 56 hz / 14 hz) 1. in the wideband mode, the loop bandwidth depends on the frequency of the reference input. for reference frequencies equal to or greater than 64 khz, the loop bandwidth = 890 hz. for reference frequencies equal to or greater than 8 khz and less than 64 khz, the loop bandwidth = 56 hz. for reference frequencies equal to 2 khz, the loop bandwidth is equal to 14 hz. phase slope limiting user se lectable: 885 ns/s, 7.5 s/s, 61 s/s, or unlimited pull-in range fixed: 130 ppm reference inputs ref0, ref1, ref2 sync inputs sync0, sync1, sync2 input reference frequencies 2 khz, n * 8 khz up to 77.76 mhz supported sync input frequencies 166.67 hz, 400 hz, 1 khz, 2 khz, 8 khz, 64 khz. input reference selection/switching automatic (based on programmable prio rity and revertiveness), or manual selection hitless reference switchin g can be enabled or disabled output clocks diff_p/n, sdh_clk, p_clk output frame pulses sdh_fp, p_fp synch ronized to active sync reference. supported output clock frequencies as listed in table 4 supported output frame pulse frequencies as listed in table 4 external pins status indicators lock, holdover table 1 - dpll features
ZL30117 data sheet 11 zarlink semiconductor inc. 1.2 dpll mode of operation the dpll supports three modes of operation - free-run, normal, and holdover. the mode of operation can be manually set or controlled by an automatic state machine as shown in figure 2. figure 2 - automatic mode state machine free-run the free-run mode occurs immediately after a reset cycl e or when the dpll has never been synchronized to a reference input. in this mode, the frequency accuracy of th e output clocks is equal to the frequency accuracy of the external master oscillator. lock acquisition the input references are continuously monitored for frequen cy accuracy and phase regularity. if at least one of the input references is qualified by the refe rence monitors, then the dpll will begi n lock acquisition on that input. given a stable reference input, the ZL30117 will enter in the normal (locked) mode. normal (locked) the usual mode of operation for the dpll is the normal mode where the dpll phase locks to a selected qualified reference input and generates output cl ocks and frame pulses with a frequency accuracy equal to the frequency accuracy of the reference input. while in the normal m ode, the dpll?s clock and frame pulse outputs comply with the mtie and tdev wander generation spec ifications as described in telc ordia and itu-t telecommunication standards. holdover when the dpll operating in the normal mode loses its refe rence input, and no other qualified references are available, it will enter the holdover mode and continue to generate output clocks based on historical frequency data collected while the dpll was synchronized. the transit ion between normal and holdover modes is controlled by the dpll so that its initial frequency offset is better than 100 ppb. the frequency drift after this transition period is dependant on the frequency drift of the external master oscillator. reset another reference is qualified and available for selection phase lock on the selected reference is achieved lock acquisition normal (locked) no references are qualified and available for selection free-run holdover selected reference fails all references are monitored for frequency accuracy and phase regularity, and at least one reference is qualified. normal (locked)
ZL30117 data sheet 12 zarlink semiconductor inc. 1.3 ref and sync inputs there are three reference clock inputs ( ref0 to ref2 ) available to the dpll. reference selection can be controlled using a built-in state machine or set in a manual mode.t he selected reference input is used to synchronize the output clocks. figure 3 - reference and sync inputs in addition to the reference inputs, the dpll has th ree optional frame pulse synchronization inputs ( sync0 to sync2 ) used to align the output frame pulses. the sync n input is selected with its corresponding ref n input, where n = 0, 1, or 2. note that the sync inpu t cannot be used to synchronize the dpll, it only determines the alignment of the frame pulse outputs. an exam ple of output frame pulse ali gnment is shown in figure 4. figure 4 - output frame pulse alignment ref2:0 sync2:0 dpll ref n diff_clk/sdh_clk/p_clk sdh/p_fp without a frame pulse signal at the sync input, the output frame pulses will align to any arbitrary cycle of its associated output clock. sync n - no frame pulse signal present when a frame pulse signal is present at the sync input, the dpll will align the output frame pulses to the output clock edge that is aligned to the input frame pulse. ref n sync n n = 0, 1, 2 n = 0, 1, 2 diff_clk/sdh_clk/p_clk sdh_fp/p_fp
ZL30117 data sheet 13 zarlink semiconductor inc. each of the ref inputs accept a single-ended lvcmos clock wi th a frequency ranging from 2 khz to 77.76 mhz. built-in frequency detection circuitry aut omatically determines the frequency of the reference if its frequency is within the set of pre-defined frequencies as shown in table 2. custom frequencies definable in multiples of 8 khz are also available. each of the sync inputs accept a single-ended lvcmos frame pulse. since alignment is determined from the rising edge of the frame pulse, there is no duty cycle restriction on this input, but there is a minimum pulse width requirement of 5 ns. frequency detection for the sync i nputs is automatic for the s upported frame pulse frequencies shown in table 3. 1.4 ref and sync monitoring all input references ( ref0 to ref2 ) are monitored for frequency accuracy and phase regularity. new references are qualified before they can be selected as a synchronization source, and qualified references are continuously monitored to ensure that they are suitable for synchron ization. the process of qualifying a reference depends on four levels of monitoring. single cycle monitor (scm) the scm block measures the period of each reference cloc k cycle to detect phase irregu larities or a missing clock edge. in general, if the measured period deviates by more than 50% from the nominal period, then an scm failure (scm_fail) is declared. 2 khz 8 khz 64 khz 1.544 mhz 2.048 mhz 6.48 mhz 8.192 mhz 16.384 mhz 19.44 mhz 38.88 mhz 77.76 mhz table 2 - set of pre-defined auto-detect clock frequencies 166.67 hz (48x 125 s frames) 400 hz 1 khz 2 khz 8 khz 64 khz table 3 - set of pre-defined auto-detect sync frequencies
ZL30117 data sheet 14 zarlink semiconductor inc. coarse frequency monitor (cfm) the cfm block monitors the reference frequency over a measurement period of 30 s so that it can quickly detect large changes in frequency. a cfm failure (cfm_fail) is triggered when the frequency has changed by more than 3% or approximately 30000 ppm. precise frequency monitor (pfm) the pfm block measures the frequency accuracy of the reference over a 10 second interval. to ensure an accurate frequency measurement, the pfm measurement inte rval is re-initiated if phase or frequency irregularities are detected by the scm or cfm. the pfm provides a level of hysteresis between the acceptance range and the rejection range to prevent a failure i ndication from toggling between valid and invalid for references that are on the edge of the acceptance range. when determining the frequency accuracy of the refe rence input, the pfm uses t he external oscillator?s output frequency (f ocsi ) as its point of reference. guard soak timer (gst) the gst block mimics the operation of an analog integrator by accumulating failure events from the cfm and the scm blocks and applying a selectable rate of decay when no failures are detected. as shown in figure 5, a gst failure (gst_fail) is triggered when the accumulat ed failures have reached the upper threshold during the disqualification observation window. when there are no cfm or scm failures, the accumulator decrements until it reaches its lower th reshold during the qu alification window. figure 5 - behaviour of the guard soak timer during cfm or scm failures sync ratio monitor all sync inputs ( sync0 to sync2 ) are continuously monitored to ensure that there is a correct number of reference clock cycles within t he frame pulse period. ref cfm or scm failures upper threshold lower threshold t d - disqualification time t q - qualification time = n * t d t d t q gst_fail
ZL30117 data sheet 15 zarlink semiconductor inc. 1.5 output clocks and frame pulses the ZL30117 offers a wide variety of outputs incl uding one low-jitter differential lvpecl clock ( diff_clk_p/n ), one sonet/sdh lvcmos ( sdh_clk ) output clock and one programmable lvcmos ( p_clk ) output clock. in addition to the clock outputs, one lvcmos sonet/sdh frame pulse output ( sdh_fp ) and one lvcmos programmable frame pulse ( p_fp ) is also available. figure 6 - output configuration the supported frequencies for the output clo cks and frame pulses are shown in table 4. diff_clk_p/n (lvpecl) sdh_clk (lvcmos) p_clk (lvcmos) sdh_fp, p_fp (lvcmos) 6.48 mhz 6.48 mhz 2 khz 166.67 hz (48x 125 s frames) 19.44 mhz 9.72 mhz n * 8 khz (up to 77.76 mhz) 400 hz 38.88 mhz 12.96 mhz 1 khz 51.84 mhz 19.44 mhz 2 khz 77.76 mhz 25.92 mhz 4 khz 155.52 mhz 38.88 mhz 8 khz 311.04 mhz 51.84 mhz 32 khz 622.08 mhz 77.76 mhz 64 khz table 4 - output clock and frame pulse frequencies dpll p_clk p_fp programmable synthesizer sdh_clk sdh_fp sonet/sdh apll diff_clk_p/n
ZL30117 data sheet 16 zarlink semiconductor inc. 1.6 configurable input-to-output and output-to-output delays the ZL30117 allows programmable static delay compensa tion for controlling input- to-output and output-to-output delays of its clocks and frame pulses. both the sonet/sdh apll and the programmable synthesizer can be configured to lead or lag the selected input reference clock using the dpll fine delay . the delay is programmed in steps of 119.2 ps with a range of -128 to +127 steps giving a total delay adjustmen t in the range of -15.26 ns to +15.14 ns. negative values delay the output clock, positive values advance the output clock. in addition to the delay introduced by the dpll fine de lay, the sonet/sdh apll and programmable synthesizer have the ability to add their ow n fine delay adjustments using the p fine delay and sdh fine delay . these delays are also programmable in steps of 119.2 p s with a range of -128 to +127 steps. in addition to these delays, the single-ended output clocks of the so net/sdh and programmable synthesizers can be independently offset by 90, 180 and 270 degrees using the coarse delay , and the sonet/sdh differential outputs can be independently delayed by -1.6 ns, 0 ns, +1.6 ns or +3.2 ns using the diff delay . the output frame pulses (sdh_clk, p_fp) can be independently offs et with respect to each other using the fp delay . figure 7 - phase delay adjustments dpll p fine delay p_clk p_fp programmable synthesizer coarse delay fp delay diff delay diff_clk_p/n sonet/sdh apll sdh_clk sdh_fp sdh fine delay coarse delay fp delay dpll fine delay feedback synthesizer
ZL30117 data sheet 17 zarlink semiconductor inc. 2.0 software configuration the ZL30117 is mainly controlled by accessing software re gisters through the serial peri pheral interface (spi). the device can be configured to operate in a highly automated manner which minimi zes its interaction with the system?s processor, or it can operate in a manual mode where the system processor controls mo st of the operation of the device. the following table provides a summary of the registers avai lable for status updates and configuration of the device. . addr (hex) register name reset value (hex) description type miscellaneous registers 00 id_reg a1 chip and version identification and reset ready indication register r 01 use_hw_ctrl 00 allows some functions of the device to be controlled by hardware pins r/w interrupts 02 ref_fail_isr ff reference failure interrupt service register r 03 dpll_isr 70 dpll interrupt service register stickr 04 reserved leave as default 05 ref_mon_fail_0 ff ref0 and ref1 failure indications stickr 06 ref_mon_fail_1 ff ref2 failure indication. stickr 07 reserved leave as default 08 reserved leave as default 09 ref_fail_isr_mask 00 reference failure interrupt service register mask r/w 0a dpll_isr_mask 00 dpll interrupt service register mask r/w 0b reserved leave as default 0c ref_mon_fail_mask_0 ff control register to mask each failure indicator for ref0 and ref1 r/w 0d ref_mon_fail_mask_1 ff control register to mask failure indicator for ref2 r/w 0e reserved leave as default 0f reserved leave as default reference monitor setup 10 detected_ref_0 ff ref0 and re f1 auto-detected frequency value status register r 11 detected_ref_1 ff ref2 auto-det ected frequency value status register r 12 reserved leave as default r 13 reserved leave as default r table 5 - register map
ZL30117 data sheet 18 zarlink semiconductor inc. 14 detected_sync_0 ee sync0 and sync1 auto-detected frequency value and sync failure status register r 15 detected_sync_1 0e sync2 auto-de tected frequency value and sync valid status register r 16 oor_ctrl_0 33 control register for the ref0 and ref1 out of range limit r/w 17 oor_ctrl_1 33 control register for the ref2 out of range limit r/w 18 reserved leave as default 19 reserved leave as default 1a gst_mask ff control register to mask the inputs to the guard soak timer for ref0 - ref2 r/w 1b reserved leave as default 1c gst_qualif_time 1a control register for the guard_soak_timer qualification time and disqualification time for the references r/w dpll control 1d dpll_ctrl_0 see register description control register for the dpll filter control; phase slope limit, bandwidth and hitless switching r/w 1e dpll_ctrl_1 see register description holdover update time, filter_out_en, freq_offset_en, revert enable r/w 1f dpll_modesel see register description control register for the dpll mode of operation r/w 20 dpll_refsel 00 dpll reference selection or reference selection status r/w 21 dpll_ref_fail_mask 3c control register to mask each failure indicator (scm, cfm, pfm and gst) used for automatic reference switching and automatic holdover r/w 22 dpll_wait_to_restore 00 control register to indicate the time to restore a previous failed reference r/w 23 dpll_ref_rev_ctrl 00 control register for the ref0 to ref2 enable revertive signals r/w 24 dpll_ref_pri_ctrl_0 10 control register for the ref0 and ref1 priority values r/w 25 dpll_ref_pri_ctrl_1 32 control register for the ref2 priority values r/w 26 reserved leave as default 27 reserved leave as default addr (hex) register name reset value (hex) description type table 5 - register map (continued)
ZL30117 data sheet 19 zarlink semiconductor inc. 28 dpll_lock_holdover_status 04 dpll lock and holdover status register r 29 reserved 03 leave as default r/w 2a - 35 reserved leave as default programmable synthesizer configuration registers 36 p_enable 8f control register to enable the p_clk and p_fp outputs of the programmable synthesizer r/w 37 p_run 0f control register to generate p_clk, p_fp r/w 38 p_freq_0 00 control register for the [7:0] bits of the n of n*8k clk r/w 39 p_freq_1 01 control register for the [13:8] bits of the n of n*8k clk r/w 3a p_clk_offset90 00 control register for the p_clk phase position coarse tuning r/w 3b reserved leave as default 3c reserved leave as default 3d p_offset_fine 00 control register for the output/output phase alignment fine tuning for the programmable synthesizer r/w 3e p_fp_freq 05 control register to select the p_fp frame pulse frequency r/w 3f p_fp_type 83 control register to select p_fp type r/w 40 p_fp_offset_0 00 bits [7:0] of the programmable frame pulse phase offset in multiples of 1/262.14 mhz r/w 41 p_fp_offset_1 00 bits [15:8] of the programmable frame pulse phase offset in multiples of 1/262.14 mhz r/w 42 p_fp_offset_2 00 bits [21:16] of the programmable frame pulse phase offset in multiples of 8 khz cycles r/w 43 - 4f reserved leave as default sdh configuration registers 50 sdh_enable 8f control register to enable sdh_clk and sdh_fp r/w 51 sdh_run 0f control register to generate sdh_clk and sdh_fp r/w 52 sdh_clk_div 42 control register for the sdh_clk frequency selection r/w 53 sdh_clk_offset90 00 control register for the sdh_clk phase position coarse tuning r/w addr (hex) register name reset value (hex) description type table 5 - register map (continued)
ZL30117 data sheet 20 zarlink semiconductor inc. 54 reserved leave as default 55 sdh_offset_fine 00 control register for the output/output phase alignrment fine tuning for sdh path r/w 56 sdh_fp_freq 05 control register to select the sdh_fp frame pulse frequency r/w 57 sdh_fp_type 23 control register to select sdh_fp type r/w 58 sdh_fp_offset_0 00 bits [7:0] of the programmable frame pulse phase offset in multiples of 1/311.04 mhz r/w 59 sdh_fp_offset_1 00 bits [15:8] of the programmable frame pulse phase offset in multiples of 1/311.04 mhz r/w 5a sdh_fp_offset_2 00 bits [21:16] of the programmable frame pulse phase offset in multiples of 8 khz cycles r/w 5b - 5f reserved leave as default differential out put configuration 60 diff_clk_ctrl a3 control register to enable diff_clk r/w 61 diff_clk_sel 53 control register to select the diff_clk frequency r/w external feedback configuration 62 reserved leave as default 63 fb_offset_fine f5 control register for the output/output phase alignment fine tuning r/w 64 reserved custom input frequencies 65 ref_freq_mode_0 00 control register to set whether to use auto detect, customa or custom b for ref0 to ref2 r/w 66 reserved leave as default 67 custa_mult_0 00 control register fo r the [7:0] bits of the custom configuration a. this is the n integer for the n*8khz reference monitoring. r/w 68 custa_mult_1 00 control register fo r the [13:8] bits of the custom configuration a. this is the n integer for the n*8khz reference monitoring. r/w 69 custa_scm_low 00 control register for the custom configuration a: single cycle scm low limiter r/w 6a custa_scm_high 00 control register for the custom configuration a: single cycle scm high limiter r/w 6b custa_cfm_low_0 00 control register for the custom configuration a: the [7:0] bits of the single cycle cfm low limit r/w addr (hex) register name reset value (hex) description type table 5 - register map (continued)
ZL30117 data sheet 21 zarlink semiconductor inc. 6c custa_cfm_low_1 00 control register for the custom configuration a: the [15:0] bits of the single cycle cfm low limit r/w 6d custa_cfm_hi_0 00 control register for the custom configuration a: the [7:0] bits of the single cycle cfm high limit r/w 6e custa_cfm_hi_1 00 control register for the custom configuration a: the [15:0] bits of the single cycle cfm high limiter r/w 6f custa_cfm_cycle 00 control register for the custom configuration a: cfm reference monitoring cycles - 1 r/w 70 custa_div 00 control register for the custom configuration a: enable the use of ref_div4 for the cfm and pfm inputs r/w 71 custb_mult_0 00 control register fo r the [7:0] bits of the custom configuration b. this is the 8 k integer for the n*8khz reference monitoring. r/w 72 custb_mult_1 00 control register fo r the [13:8] bits of the custom configuration b. this is the 8 k integer for the n*8khz reference monitoring. r/w 73 custb_scm_low 00 control register for the custom configuration b: single cycle scm low limiter r/w 74 custb_scm_high 00 control register for the custom configuration b: single cycle scm high limiter r/w 75 custb_cfm_low_0 00 control register for the custom configuration b: the [7:0] bits of the single cycle cfm low limiter. r/w 76 custb_cfm_low_1 00 control register for the custom configuration b: the [15:0] bits of the single cycle cfm low limiter. r/w 77 custb_cfm_hi_0 00 control register for the custom configuration b: the [7:0] bits of the single cycle cfm high limiter. r/w 78 custb_cfm_hi_1 00 control register for the custom configuration b: the [15:0] bits of the single cycle cfm high limiter. r/w 79 custb_cfm_cycle 00 control register for the custom configuration b: cfm reference monitoring cycles - 1 r/w 7a custb_div 00 control register for the custom configuration b: enable the use of ref_div4 for the cfm and pfm inputs r/w addr (hex) register name reset value (hex) description type table 5 - register map (continued)
ZL30117 data sheet 22 zarlink semiconductor inc. 3.0 references advancedtca, atca and the advancedtca and atca logo s are trademarks of the pci industrial computer manufacturers group. 7b - 7f reserved addr (hex) register name reset value (hex) description type table 5 - register map (continued)
c zarlink semiconductor 2005 all rights reserved. issue apprd. date acn package code previous package codes
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